Within the field of circuits and semiconductors, various electrical features of different circuit devices, such as field effect transistors (FETs), metal-oxide-semiconductor FETs (MOSFETs), etc., can be used to determine chip power optimization of the circuit device. For example, various types of FETs include structure that comprises a gate, source, and drain. When the gate voltage of a FET device (i.e., the voltage difference between the gate and the source of the FET device) is larger than the threshold voltage of the FET, electric current (also called drain current) can travel from the source to the drain. However, when the gate voltage applied to the FET is less than the threshold voltage, there is not a significant amount of current traveling from the source to the drain.
There are instances that when the gate voltage applied to the FET is less than the threshold voltage, or even when there is no voltage applied to the gate, an amount of current still passes between the source and drain. This amount of current is known as the leakage current and can affect the total chip power dissipation for a device. The leakage current, also known as Iddq current, can be caused by various factors, such as diffusion, random doping fluctuation (RDF), line edge roughness (LER), etc. When a FET device contains multiple individual FET devices that are connected in parallel (often called an ensemble FET; examples include multi-finger planar FET, a finFET device containing multiple fins), other issues can exist relating to determining the leakage current. For example, the variation of the leakage current in one FET device can be uncorrelated to the leakage current in another individual FET where the two FETs are part of an ensemble device.